Devices and methods for autonomous hardware management of circular buffers

ABSTRACT

An autonomous circular buffer is described in connection with the various embodiments of the present disclosure. An autonomous circular buffer controller may control movement of data between a user of the autonomous circular buffer and a peripheral. The autonomous circular buffer may enable direct memory access type data movement, including between the user and the peripheral.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(e) of U.S.Provisional Patent Application Ser. No. 62/458,362, filed Feb. 13, 2017,the entire contents and disclosure of which is hereby incorporatedherein by this reference.

TECHNICAL FIELD

Embodiments of the present disclosure relate generally to direct memoryaccess control and more specifically to autonomous control of memoryaccesses to circular buffers for direct memory access.

BACKGROUND

In many embedded control systems and other computing systems movement ofdata between peripheral devices and a host, or between peripheraldevices, may be a significant amount of data traffic on the variousbusses that may exist in such systems. Direct Memory Access (DMA)controllers may be used to manage these data transfers so the host doesnot need to manage movement of each data element. However, conventionalDMA controllers still have significant overhead management that a hostneeds to perform and DMA controllers are generally more efficient onlywith bulk data transfers.

BRIEF SUMMARY

Various embodiments relate to methods of accessing data in memory. Themethods may include allocating a circular buffer region of the memoryfor use by an autonomous circular buffer controller; transferring inputdata elements to the circular buffer region at subsequent inputlocations pointed at by an input pointer; and transferring output dataelements from the circular buffer region at subsequent output locationspointed at by an output pointer. In one embodiment, each of the inputpointer and the output pointer are configured to: update to point to anext data element location in the circular buffer region responsive toaccess to a current data element location; and wrap around to abeginning address of the circular buffer region responsive to an endingaddress of the circular buffer region being reached.

Other embodiments described herein relate to a system. The system mayinclude a first interface, a second interface and an autonomous circularbuffer controller. The first interface may be configured to communicateon a first bus for operable coupling with one or more peripheral devicesand a host processor. The second interface may be configured tocommunicate on a second bus for operable coupling with a memory. Theautonomous circular buffer controller may be configured to define andaccess a circular buffer region of the memory. The autonomous circularbuffer may be further configured to: control a head pointer for steppingthrough the circular buffer region and wrapping around from an endingaddress to a beginning address; control a tail pointer for steppingthrough the circular buffer region and wrapping around from the endingaddress to the beginning address; move a first data element from thefirst interface to a location in the circular buffer region pointed atby the head pointer; and move a second data element from a location inthe circular buffer region pointed at by the tail pointer to the firstinterface.

Other embodiments described herein relate to a system. The system mayinclude a host processor, one or more peripherals, a first interface,and an autonomous circular buffer controller. The first interface may beconfigured to communicate on a first bus for operable coupling with theone or more peripheral devices and the host processor. The autonomouscircular buffer controller may be configured to define and access acircular buffer region of the memory. The autonomous circular buffer maybe further configured to: control a head pointer for stepping throughthe circular buffer region and wrapping around from an ending address toa beginning address; control a tail pointer for stepping through thecircular buffer region and wrapping around from the ending address tothe beginning address; and move a first data element from a location inthe circular buffer region pointed at by the tail pointer to the firstinterface.

Other embodiments described herein relate to a system. The system mayinclude a host processor, a first peripheral device and a secondperipheral device. The second peripheral device may comprise a firstinterface configured to communicate on a bus operably coupled to thehost processor and the first peripheral. In one embodiment, the secondperipheral device is configured to provide a multichannel autonomouscommunication path between the host processor and first peripheral.

BRIEF DESCRIPTION OF THE DRAWINGS

Purposes and advantages of the embodiments of the disclosure will beapparent to one of ordinary skill in the art from the detaileddescription in conjunction with the accompanying drawings, including:

FIG. 1 is a block diagram of a universal synchronous/asynchronousreceiver/transmitter configured as a receiver.

FIG. 2 is a conceptual diagram illustrating a circular buffer.

FIG. 3 is a block diagram of a computing system including a hostprocessor, memory, a peripheral device, and an autonomous circularbuffer controller.

FIG. 4 is a detailed block diagram of the autonomous circular buffercontroller.

FIG. 5 illustrates an example memory map showing a circular bufferregion in a memory map.

FIG. 6 is a flow diagram illustrating processes associated withconfiguring and using the autonomous circular buffer.

FIGS. 7A and 7B are block diagrams of an autonomous circular buffercontroller that shows data movement.

FIG. 8 is a block diagram of an autonomous communication path between aCPU and a peripheral.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which are shown,by way of illustration, specific example embodiments in which thepresent disclosure may be practiced. These embodiments are described insufficient detail to enable a person of ordinary skill in the art topractice the present disclosure. However, other embodiments may beutilized, and structural, material, and process changes may be madewithout departing from the scope of the disclosure. The illustrationspresented herein are not meant to be actual views of any particularmethod, system, device, or structure, but are merely idealizedrepresentations that are employed to describe the embodiments of thepresent disclosure. The drawings presented herein are not necessarilydrawn to scale. Similar structures or components in the various drawingsmay retain the same or similar numbering for the convenience of thereader; however, the similarity in numbering does not mean that thestructures or components are necessarily identical in size, composition,configuration, or any other property.

It will be readily understood that the components of the embodiments asgenerally described herein and illustrated in the drawing could bearranged and designed in a wide variety of different configurations.Thus, the following description of various embodiments is not intendedto limit the scope of the present disclosure, but is merelyrepresentative of various embodiments. While the various aspects of theembodiments may be presented in drawings, the drawings are notnecessarily drawn to scale unless specifically indicated.

Furthermore, specific implementations shown and described are onlyexamples and should not be construed as the only way to implement thepresent disclosure unless specified otherwise herein. Elements,circuits, and functions may be shown in block diagram form in order notto obscure the present disclosure in unnecessary detail. Conversely,specific implementations shown and described are exemplary only andshould not be construed as the only way to implement the presentdisclosure unless specified otherwise herein. Additionally, blockdefinitions and partitioning of logic between various blocks isexemplary of a specific implementation. It will be readily apparent toone of ordinary skill in the art that the present disclosure may bepracticed by numerous other partitioning solutions. For the most part,details concerning timing considerations and the like have been omittedwhere such details are not necessary to obtain a complete understandingof the present disclosure and are within the abilities of persons ofordinary skill in the relevant art.

Those of ordinary skill in the art would understand that information andsignals may be represented using any of a variety of differenttechnologies and techniques. For example, data, instructions, commands,information, signals, bits, symbols, and chips that may be referencedthroughout this description may be represented by voltages, currents,electromagnetic waves, magnetic fields or particles, optical fields orparticles, or any combination thereof. Some drawings may illustratesignals as a single signal for clarity of presentation and description.It will be understood by a person of ordinary skill in the art that thesignal may represent a bus of signals, wherein the bus may have avariety of bit widths and the present disclosure may be implemented onany number of data signals including a single data signal.

The various illustrative logical blocks, modules, and circuits describedin connection with the embodiments disclosed herein may be implementedor performed with a general-purpose processor, a special-purposeprocessor, a Digital Signal Processor (DSP), an Application SpecificIntegrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) orother programmable logic device, discrete gate or transistor logic,discrete hardware components, or any combination thereof designed toperform the functions described herein. A general-purpose processor (mayalso be referred to herein as a host processor or simply a host) may bea microprocessor, but in the alternative, the processor may be anyconventional processor, controller, microcontroller, or state machine. Aprocessor may also be implemented as a combination of computing devices,such as a combination of a DSP and a microprocessor, a plurality ofmicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other such configuration. A general-purpose computerincluding a processor is considered a special-purpose computer while thegeneral-purpose computer is configured to execute computing instructions(e.g., software code) related to embodiments of the present disclosure.

Also, it is noted that the embodiments may be described in terms of aprocess that is depicted as a flowchart, a flow diagram, a structurediagram, or a block diagram. Although a flowchart may describeoperational acts as a sequential process, many of these acts may beperformed in another sequence, in parallel, or substantiallyconcurrently. In addition, the order of the acts may be re-arranged. Aprocess may correspond to a method, a thread, a function, a procedure, asubroutine, a subprogram, etc. Furthermore, the methods disclosed hereinmay be implemented in hardware, software, or both. If implemented insoftware, the functions may be stored or transmitted as one or moreinstructions or code on computer-readable media. Computer-readable mediaincludes both computer storage media and communication media includingany medium that facilitates transfer of a computer program from oneplace to another.

It should be understood that any reference to an element herein using adesignation such as “first,” “second,” and so forth does not limit thequantity or order of those elements, unless such limitation isexplicitly stated. Rather, these designations may be used herein as aconvenient method of distinguishing between two or more elements orinstances of an element. Thus, a reference to first and second elementsdoes not mean that only two elements may be employed there or that thefirst element must precede the second element in some manner. Inaddition, unless stated otherwise, a set of elements may comprise one ormore elements.

Elements described herein may include multiple instances of the sameelement. These elements may be generically indicated by a numericaldesignator (e.g., 110) and specifically indicated by the numericalindicator followed by an alphabetic designator (e.g., 110A) or a numericindicator preceded by a “dash” (e.g., 110-1). For ease of following thedescription, for the most part element number indicators begin with thenumber of the drawing on which the elements are introduced or most fullydiscussed. Thus, for example, element identifiers on a FIG. 1 will bemostly in the numerical format 1xx and elements on a FIG. 4 will bemostly in the numerical format 4xx.

As used herein, the term “substantially” in reference to a givenparameter, property, or condition means and includes to a degree thatone of ordinary skill in the art would understand that the givenparameter, property, or condition is met with a small degree ofvariance, such as, for example, within acceptable manufacturingtolerances. By way of example, depending on the particular parameter,property, or condition that is substantially met, the parameter,property, or condition may be at least 90% met, at least 95% met, oreven at least 99% met.

Reference throughout this specification to “one embodiment,” “anembodiment,” or similar language means that a particular feature,structure, or characteristic described in connection with the indicatedembodiment is included in at least one embodiment of the presentdisclosure. Thus, the phrases “in one embodiment,” “in an embodiment,”and similar language throughout this specification may, but do notnecessarily, all refer to the same embodiment.

Embodiments described herein include autonomous hardware management ofcircular buffers in memory. The circular buffers are accessible by ahost processor, one or more peripheral devices, or a combinationthereof, without direct reference to the addresses of the circularbuffer in memory. An autonomous circular buffer controller according toembodiments of the present disclosure may be configured to control atemporary storage that ensures an efficient asynchronous transfer ofdata between software tasks and hardware devices or between two hardwaredevices.

Most, if not all, embedded systems use buffering of data, usually in aseparate memory. Buffering may be used to relax real time requirements,but may also be used to ensure sustainable throughput. In some systems,buffering may be implemented in hardware using a Direct Memory Access(DMA) controller, or in software.

DMA buffering is efficient in its general use of block data transfers,where a relatively large block of data is prepared before it is moved.The DMA process may be set up, after which the DMA process and hardwarewill handle the data movement to or from memory (e.g., between aperipheral such as a serial communication peripheral and a memory). ThisDMA process off-loads the host processor efficiently, but has overheadassociated with managing the DMA controller, the buffers in memory, anddetermining when it is appropriate to perform the DMA operations. As aresult, DMA processes only tend to be efficient for larger data chunks.Further, it is generally not feasible to start a DMA transfer until theentire data package is prepared, which may cause significant latency inthe transfer and may subsequently mean that it is not possible to keep asustained high throughput when using DMA. In addition, the bufferingwhen using DMA is linear, meaning the DMA starts reading/writing from astart address, and stops when it comes to the end of the block, as thisis when the transfer is completed.

When implementing buffering in software, linear buffers are also anoption, but a circular buffer is usually more attractive as data may bewritten continuously to the circular buffer while data is being readfrom the circular buffer. Moreover, a circular buffer may handle burstblocks of data arriving or leaving like a conventional DMA process, butmay also handle streaming data that may arrive or leave the circularbuffer at more regular time intervals.

FIG. 1 is a block diagram of a Universal Synchronous/AsynchronousReceiver/Transmitter (USART) 100 configured as a receiver. Some systemsare designed so that a certain level of buffering is added to theperipherals. This USART 100 includes a relatively small form of doublebuffering in the receive direction. The USART 100 includes a single-bytebuffer (not shown) in a transmit direction, and a two-byte buffer 102 ina receive direction. This buffering relaxes the fundamental real-timerequirements for communication between the serial bit-wise nature of aperipheral device and a host processor. Nevertheless, most peripheraldrivers would still use additional buffering to reduce overheadrequirements on the host processor.

FIG. 2 is a conceptual diagram illustrating a circular buffer 200. Acircular buffer 200 may be implemented as a First-In-First-Out (FIFO)buffer. The lightly shaded blocks 204 indicate locations that includevalid data elements in the circular buffer. The darkly shaded block 203indicate locations that are empty or locations where data elements havealready been removed from the circular buffer 200.

A head pointer 201 (may also be referred to herein as an “inputpointer”) points to the most recently written data element. In thiscase, the head pointer 201 will be incremented (or decremented) to pointto the next available location before the next input data element iswritten to the circular buffer 200. Alternatively, the head pointer 201may be configured to point to the next available data location forwriting to the circular buffer 200 (i.e., the location labeled x_(n)-11,which currently contains already removed data). In this case, the headpointer 201 will be incremented (or decremented) to point to the nextavailable location after the current input data element is written tothe circular buffer 200.

A tail pointer 202 (may also be referred to herein as an “outputpointer”) points to the location holding the oldest valid data elementin the circular buffer 200 that is available for reading. In this case,the tail pointer 202 will be incremented (or decremented) to point tothe next available location after the current output data element isread from the circular buffer 200.

In conventional systems, if a task or function in software running on ahost processor writes a string to a USART such as the USART 100 shown inFIG. 1, the function would have to wait for the USART 100 to transmitthe string until code execution may continue if not buffered. It is a socalled “busy-wait” situation that stalls the program execution andimpacts the real time performance of the system.

In contrast, if the function writing the string may write the string toa circular buffer such as a circular buffer 200, then a USART interruptroutine may fetch a new character from the circular buffer 200 wheneverthe USART 100 is ready to transfer the next byte. However, an issue witha conventional circular buffer is that the host processor still has tomanage the circular buffer 200, which may cause unavoidable codeoverhead, both when writing data to the circular buffer 200 and whenreading it out again.

FIG. 3 is a block diagram of a computing system 300 including a hostprocessor 304, memory 303 (SRAM), a peripheral device 302, and anautonomous circular buffer (ACB) controller 301. As non-limitingexamples, the computing system 300 may be a microcontroller-typeembedded system, a user-type computer, a file server, a compute server,a notebook computer, a tablet, a handheld device, a mobile device, orother similar computer system for executing software. Computer,computing system, and server may be used interchangeably herein toindicate a system for practicing embodiments of the present disclosure.The computing system 300 is configured for executing software programscontaining computing instructions and includes one or more processors,memory, storage, user interface elements, and one or more communicationelements.

The host processor 304 is a Central Processing Unit (CPU) that may beconfigured for executing a wide variety of operating systems andapplications including computing instructions for carrying out all orportions of embodiments of the present disclosure.

The memory 303 may be used to hold computing instructions, datastructures, and other information for performing a wide variety of tasksincluding performing embodiments of the present disclosure. By way ofexample, and not limitation, the memory may include Synchronous RandomAccess Memory (SRAM), Dynamic RAM (DRAM), Read-Only Memory (ROM), Flashmemory, and the like.

The memory 303 may include other types of memory devices, includingvolatile storage devices or non-volatile storage devices, configured tostore information. Examples of other types of memory include nano RAM or(NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10nanometer process memory, graphene memory,Silicon-Oxide-Nitride-Oxide-Silicon (SONOS), Resistive random-accessmemory (RRAM), programmable metallization cell (PMC),conductive-bridging RAM (CBRAM), magneto-resistive RAM (MRAM), phasechange RAM (PCRAM), phase change memory, or other solid-state storagemedia.

In the illustrated embodiment, the host device (i.e., CPU) 304communicates with a memory 303 (i.e., SRAM) on an SRAM bus 306. Also,the CPU 304 communicates with peripheral devices 302 on a peripheral bus305. The peripheral devices 302 may also be coupled to an event systembus 307. Additional details regarding one type of event system and eventbus, as well as overall microcontroller system configurations, may befound in U.S. Pat. No. 9,256,399 entitled “BREAKING PROGRAM EXECUTION ONEVENTS,” filed on Jun. 27, 2013, the disclosure of which is incorporatedherein in its entirety by this reference.

The ACB controller 301 is configured to communicate on the SRAM bus 306,the peripheral bus 305, and the event system bus 307.

Of course, a person having ordinary skill in the art will recognize thatembodiments of the present disclosure may be used in other systemconfigurations. For example, embodiments may be configured in a computertype system using an interrupt type system for the event controls.Moreover, this type of system may have a separate bus (e.g., anInput/Output bus) for communication between the CPU 304 and anyperipheral devices 302. In addition, this type of system may include theACB controller 301 as communicating on the memory bus (i.e., SRAM bus)306, which may be coupled directly with the memory 303 and CPU 304, andcommunication with the peripheral devices 302 on such an I/O bus.

Many other system configurations are possible for embodiments of thepresent disclosure. Additional details regarding one type ofmicrocontroller system configuration, may be found in U.S. Pat. No.8,402,180 entitled “AUTONOMOUS MULTI-PACKET TRANSFER FOR UNIVERSALSERIAL BUS,” filed on Mar. 26, 2010, the disclosure of which isincorporated herein in its entirety by this reference.

FIG. 3 is a detailed block diagram of the ACB controller 301, inaccordance with embodiments of the present disclosure. The ACBcontroller 301 may be configured as a controller for temporary storagethat ensures an efficient asynchronous (or synchronous) transfer of databetween software tasks and hardware devices or between two hardwaredevices (for example, two peripherals).

In short, while DMA is good for large blocks of data, it lacks thecapability and/or has drawbacks when handling single bytes like acircular buffer and misses the capability of initiating the data movebefore an entire package has been assembled. Software implementedcircular buffers may include significant overhead to handle both writeto and read from pointers and processes. Moreover, software implementedcircular buffers do not, like the DMA, handle the transaction to/from aperipheral autonomously (e.g., without oversight by a host processor).

With the ACB controller 301 of the present disclosure, overheadprocesses that might have been handled by the CPU 304 of the controlsystem 300 may be off-loaded by implementing an ACB in hardware that mayoperate in close collaboration with other peripherals, such ascommunication modules, timers, Analog-to-Digital Controllers (ADCs) andDigital-to-Analog Controllers (DACs). Such an ACB may act similar to atraditional DMA (i.e., be set up to handle linear data) and it may beset up to “wrap” once the end of the data has been reached and startover again. This process may be particularly useful when generatingwaveforms from, for example, a DAC.

Note that an ACB controller and circular buffer region in memory may becollectively referred to herein as an autonomous circular buffer (ACB).

In embodiments of the present disclosure, the ACB controller 301controls a circular buffer in memory 303 (or another memory) that isinserted between the peripheral 302 and the CPU 304, so that instead ofletting the CPU 304 write to the peripheral 302, the CPU 304 writes tothe circular buffer. When the peripheral 302 is ready to receive data,the ACB controller 301 may move data from the circular buffer in memory303 to the destination (e.g., the peripheral device 302) as long asthere is data in the circular buffer. These transfers from the CPU 304to the circular buffer and from the circular buffer to the peripheral302 may occur sequentially or may occur in parallel as long as there isvalid data in the circular buffer.

Of course, transfers may happen the other direction. In other words, theACB controller 301 may move data coming from the peripheral device 302to the circular buffer and from the circular buffer to the CPU 304.

An ACB controller 301 may not automatically transfer all the data to adestination, but rather manage the circular buffer and thereby reducethe software overhead significantly. In that configuration an ACB may beaccessed as a peripheral module: it is possible to read or write bytesthrough a register interface, while the DMA functionality of the ACB(i.e., the ACB controller 301) is actually storing/fetching the datain/from an SRAM (i.e., memory 303) fully transparently to the softwareprocess on the CPU 304. The CPU 304 does not need to relate to an actualmemory access operation to the SRAM. Rather, the CPU just writes to, orreads from, one specific address in the ACB.

Turning to FIG. 4, for example, in a peripheral to host data transfer, aperipheral writes to the ACB_DATA_WRITE register 402. A write databuffer 407 may be coupled to the ACB_DATA_WRITE register 402 to hold thedata before it is written to the circular buffer region in SRAM. ACBcontroller 420 may use a value in the buffer head register 422 to writethe data to the proper location in the circular buffer region of theSRAM. The data may come from the data buffer 407, if present, ordirectly from the ACB_DATA_WRITE register 402. Incrementing,decrementing, and wrap-around of the Buffer head register 422 isexplained above with reference to FIG. 2 and supplemented with thedescription below with reference to FIG. 5.

In the background (i.e., not seen or managed by the host or peripheral),the ACB controller 420 may use a value in the buffer tail register 423to read data from the proper location in the circular buffer region ofthe SRAM. The data may be placed in a read data buffer 408, if present,or directly in an ACB_DATA READ register 403. Incrementing,decrementing, and wrap-around of the buffer tail register 423 isexplained above with reference to FIG. 2 and supplemented with thedescription below with reference to FIG. 5.

When the host begins to read data it reads only from the ACB_DATA_READregister 403 with the ACB controller 420 managing all the accesses fromthe circular buffer region of the SRAM and providing the data throughthe ACB_DATA_READ register 403.

Data movement may also occur in the other direction from the host to theperipheral device. In such cases, the host writes to the ACB_DATA_WRITEregister 402 and the peripheral device reads from the ACB_DATA_READregister 403.

Finally, data movements may occur between two peripheral devices ratherthan between a peripheral device and the host.

The ACB controller 420 may include registers to indicate where in memorythe ACB controller 420 should place the circular buffer region. As oneexample, the registers may include a buffer start register 424 and abuffer size register 425 as shown in FIG. 4. Other embodiments may use abuffer end register rather than a buffer size register 425, or any othercombination of registers to identify the extents of the circular buffer.

ACB 400 may include a status register 404 that provides informationabout available room in the circular buffer, number of bytes stored inthe circular buffer, and so on. A vacancy counter 405 may be included toindicate how many data elements in the circular buffer are not presentlyused. Similarly, a fill counter 406 may be included to indicate how manydata elements in the circular buffer currently include valid data.

The ACB 400 may include a control or command register 401 and the ACBcontroller 420 may include a command interpreter 421 that may be used tocontrol the access type (e.g., peek, write/read leading data element,write/read tailing data element, etc.).

The ACB controller 420 is thus able to collaborate with the peripherals.For example, the ACB controller 420 “understands” the state of aperipheral, and thereby knows if a peripheral is ready to transmitoutput data. Similarly, the ACB controller 420 “understands” if aperipheral has received new data, and may collect this data and place itin the circular buffer. On reception, the ACB controller 420 may beconfigured to notify a CPU (or another peripheral) that new data isavailable, and a CPU may then inspect the status register 404 to knowhow much data is available and collect the data from the ACB 400. TheACB controller 420 may be set up to use the event system 411 to notifythe CPU or peripheral on each data element or for a package of a givensize.

An extension of the ACB controller 420 may be configured to make itprotocol aware, by configuring it so that it knows which byte(s) in theprotocol contains information about the package size and the datalocation within the packet. This may allow the ACB 400 to only interrupta CPU when an entire package is received, and thus save CPU bandwidthand reduce power consumption.

FIG. 5 is an example memory map 500 showing a circular buffer region 501in a memory map. The circular buffer region 501 extends from an ACBbuffer start location 502 to an ACB buffer end location 503. A tailpointer 504 points to the next available location 505 for reading dataand head pointer 506 points to the next available write location 507.

A lightly shaded region shows a vacant region 508 within the circularbuffer region 501 and darkly shaded regions show populated regions 509in the circular buffer region 501 that include currently valid data.Thus, one may see that the head pointer 506 has reached the end of thecircular buffer region 501 and has wrapped around to the buffer startlocation 502 and filled in data from the buffer start location 502 up tothe current head pointer location 507. As the tail pointer 504increments when data is read out, the tail pointer 504 will also wraparound to the buffer start location 502 to continue reading valid datafrom the populated region 509.

The example in FIG. 5 shows the tail pointer and head pointerincrementing for each data access and wrapping around from the bufferend to the buffer start. Alternatively, the tail pointer and headpointer could be configured to decrement and wrap from the buffer startto the buffer end.

FIG. 6 is a flow diagram illustrating processes associated withconfiguring and using the autonomous circular buffer. At process block602, the CPU initializes the ACB controller by setting up a buffer startaddress and size and the input event channel. At process block 604 theCPU initializes a USART peripheral and sets the output event channel.

At process block 606 the CPU writes a character string “Hello world” tothe ACB data write register. The ACB controller then stores thecharacter string in the circular buffer region of the SRAM.

At process block 608 the ACB controller transfers a byte from the SRAMto the USART peripheral. Decision block 610 indicates a test to see if aUSART peripheral event has occurred. If not, the process loops to waitfor the event.

If the event has occurred, decision block 612 indicates a test to see ifthere is more valid data in the circular buffer region of the SRAM. Ifso, the process loops back to process block 608 to transfer additionaldata to the USART.

If the circular buffer region of the SRAM is empty, process block 614indicates that the transaction is complete and an optional interrupt maybe sent to the CPU.

FIGS. 7A and 7B are detailed block diagrams of an ACB 700 that includesan ACB controller 720 implementing an N-level first-in-first-out (FIFO)buffer 702 in RAM, in accordance with embodiments of the presentdisclosure.

FIG. 7A shows the direction of data movement in a READ operation, i.e.,where a CPU (not shown) writes data to the ACB 700 as if it is aperipheral and the peripheral 704 receives data from the ACB 700. Whenthe peripheral 704 is ready to receive data, the ACB controller 720 maymove data from the buffer 702 to a data register 705 of the peripheral704 as long as there is data in the buffer 702. The transfers from a CPUto the ACB 700 and from the ACB 700 to the peripheral 704 may occursequentially or may occur in parallel as long as there is valid data inthe buffer 702. In one embodiment, the ACB controller 720 does notimmediately transfer the data to the peripheral 704, but waits totransfer the data upon receiving an event notification that theperipheral 704 is available.

For example, in a user (e.g., a CPU) to peripheral data transfer, theuser writes to the FIFO data register 703. In one embodiment, the ACBcontroller 720 may include a control register (CCRx) 725, and may updateone or more control register bits (or bytes) 726, e.g., TRG, DSZ, DIR,and ADR. In one embodiment, the control register bits 726 may beconfigured to be a status interface. In one embodiment, the ACBcontroller 720 may represent several channels and may use alook-up-table 727 responsive to a channel identifier (e.g., PTID) toaccess the control bits 726.

In one embodiment, the value in the DSZ register may indicate the sizeof the data to be read from the buffer 702; the value in the DIRregister may indicate the direction of the data transfer (e.g., CPUread/CPU write); the value in the ADR register may indicate the addressof the peripheral's data register 705; and the value in the TRG registermay indicate the event channel used to trigger the transfer.

The ACB controller 720 may set up the buffer 702 based on values storedat the FIFO_IN register 723, FIFO_OUT register 722 and FIFO_SIZEregister 724. The value in the FIFO_IN register 723 is indicative of abuffer tail pointer and the value in the FIFO_OUT register 722 isindicative of a buffer head pointer.

The ACB controller 720 may use a value in the FIFO_IN register 723 towrite the data to the proper location in the buffer 702 of the RAM. Thedata may come from the FDR 703. The ACB controller 720 may use the datain the DIR register to determine that there is data available to readfrom the FDR 703 and write to the buffer 702. The ACB controller 720 maywrite the data in the buffer 702 to the peripheral's data register 705responsive to the value in the TRG control register. When the peripheral704 is ready, the ACB controller 720 may use an address in the ADRregister to write the data to the proper data register 705 of theperipheral 704.

In various embodiments, one or more of the control bits of the controlregister 726 of the ACB controller 720 (e.g., DSZ, DIR, ADR) may beavailable to the peripheral or CPU, for example, in a peek( ) operation.

FIG. 7B shows the direction of data movement in a WRITE operation, i.e.,the ACB controller 720 moves data coming from the peripheral 704 to thebuffer 702 and from the buffer 702 to a CPU. Responsive to receiving acommand ‘PTID’ and comparing it to entries in a look-up-table 727, theACB controller 720 may update one or more control bit registers 726,TRG, DSZ, DIR, and ADR.

The ACB controller 720 may use a value in the FIFO_IN register 723 towrite the data to the proper location in the buffer 702 of the RAM. Thedata may come from the peripheral's data register 705. The ACBcontroller 720 may use the data in the DIR register to determine thatthere is data available to read from the buffer 702, and use the valuesin the FIFO_OUT register 722 and DSZ register to read the data from theproper locations in the buffer 702 of the RAM. The ACB controller 720may write the data read from the buffer 702 to the FIFO data register703. In one embodiment, an optional interrupt may be asserted toindicate to the CPU that the data is available in the FIFO data register703.

An ACB controller 720 described with reference to FIGS. 7A and 7B may beused to implement an autonomous communication path between two users.FIG. 8 is a block-diagram of an n-channel autonomous communication path(ACP) 801 between CPU 802 and RAM 803 on one side and a USART 804. Eachchannel may be an ACB 700 and ACB 720 of the type shown in FIGS. 7A and7B, respectively. The USART has bi-directional communicationrequirements, and so at least one channel of the ACP 801 may facilitateread communication and at least one other channel of the ACP 801 mayfacilitate substantially simultaneous write communication. Communicationmay be initiated responsive to a CPU issuing a DMA request for datatransfer from the SRAM 803 to the USART 804. The ACP 801 handles theread/write operations, saving the CPU from the burdensome task oftransferring using programmed I/O that are typically too small tojustify the set-up overhead for a conventional DMA controller.

The ACP 801 may be used with any peripheral that includes a buffer orwould benefit from a buffer. Additional channels may be added as needed,including to implement control features for the other channels (e.g.,transferring a descriptor for the next DMA request in the queue).

While FIG. 8 shows multi-channel communication between two users, insome embodiments, the ACP may facilitate communication from one to manydestinations, e.g., each channel may be configured to facilitatecommunication to a number of different peripherals. The ACP may alsofacilitate communication from many to one destination. In anotherembodiment, the ACP may be configured to enable high-bit-ratecommunication by providing several channels that may be simultaneouslywritten to and read from, for example, between two peripherals.

A person having ordinary skill in the art would recognize that thisprocess could move data in the other direction from a peripheral deviceto the CPU. Alternatively, the process could move data between twoperipheral devices. It should also be pointed out that while notdirectly illustrated, data movement in process block 606 and datamovement in process block 608 may overlap such that some of thecharacter string “Hello world” may begin moving to the USART before thecharacter string is fully written by the CPU.

For the most part, data movement has been discussed herein in terms ofbytes. However, embodiments of the present disclosure may be configuredwith many other sizes for individual data elements such as, for example,16-bit words, 32-bit words, 64-bit words, and DRAM burst-length dataelements.

In summary, in embodiments of the present disclosure, a CPU is offloadedfrom handling buffering in software, which impacts the maximumthroughput, and affects the real time performance of the system.Further, implementing an ACB controller allows a CPU to enter low powermode during transmissions.

Thus, an ACB controller may reduce power consumption, increasesustainable throughput, and improve system responsiveness as the CPU isnot stalled for polling and not busy performing other buffer managementprocesses. The ACB controller may eliminate undetectedbuffer-over/underrun situations and perform faster buffer read/writes.

With the ACB controller, a register interface simplifies access, buffermanagement is handled in hardware (head/tail pointers etc.), and supportmay be provided for typical functions such as get( ) put( ) peek( )flush( ) and so on. SRAM may be used to store data and a DMA-likefunctionality moves data from ACB registers to a circular buffer inSRAM.

The ACB controller may improve access and add buffering to manyperipherals to improve many embedded control functions such as DAC, ADC,and pulse-width modulation controls.

An ACB controller: automates data-moves to/from peripherals, relaxesreal-time requirements, improves system response time due to fewerinterrupts, enables increased and sustained through-put on communicationperipherals, enables advanced waveform generation with minimal CPUintervention, allows sophisticated interaction between peripherals(e.g., if ADC result>x, load next value pulse width modulated (PWM)signal into a DAC).

Many of the functional units described in this specification may belabeled as modules, threads, or other segregations of programming code,in order to more particularly emphasize their implementationindependence. Modules may be at least partially implemented in hardware,in one form or another. For example, a module may be implemented as ahardware circuit comprising custom VLSI circuits or gate arrays,off-the-shelf semiconductors such as logic chips, transistors, or otherdiscrete components. A module may also be implemented in programmablehardware devices such as field programmable gate arrays, programmablearray logic, programmable logic devices, or the like.

Modules may also be implemented using software, stored on a physicalstorage device (e.g., a computer-readable storage medium), in memory, ora combination thereof for execution by various types of processors.

An identified module of executable code may, for instance, comprise oneor more physical or logical blocks of computer instructions, which may,for instance, be organized as a thread, object, procedure, or function.Nevertheless, the executables of an identified module need not bephysically located together, but may comprise disparate instructionsstored in different locations which, when joined logically together,comprise the module and achieve the stated purpose for the module.

Indeed, a module of executable code may be a single instruction, or manyinstructions, and may even be distributed over several different codesegments, among different programs, and across several storage or memorydevices. Similarly, operational data may be identified and illustratedherein within modules, and may be embodied in any suitable form andorganized within any suitable type of data structure. The operationaldata may be collected as a single data set, or may be distributed overdifferent locations including over different storage devices, and mayexist, at least partially, merely as electronic signals on a system ornetwork. Where a module or portions of a module are implemented insoftware, the software portions are stored on one or more physicaldevices, which are referred to herein as computer-readable media.

In some embodiments, the software portions are stored in anon-transitory state such that the software portions, or representationsthereof, persist in the same physical location for a period of time.Additionally, in some embodiments, the software portions are stored onone or more non-transitory storage devices, which include hardwareelements capable of storing non-transitory states and/or signalsrepresentative of the software portions, even though other portions ofthe non-transitory storage devices may be capable of altering and/ortransmitting the signals. One example of a non-transitory storage deviceincludes a read-only memory (ROM), which may store signals and/or statesrepresentative of the software portions for a period of time. However,the ability to store the signals and/or states is not diminished byfurther functionality of transmitting signals that are the same as orrepresentative of the stored signals and/or states. For example, aprocessor may access the ROM to obtain signals that are representativeof the stored signals and/or states in order to execute thecorresponding software instructions.

While the present disclosure has been described herein with respect tocertain illustrated embodiments, those of ordinary skill in the art willrecognize and appreciate that the present invention is not so limited.Rather, many additions, deletions, and modifications to the illustratedand described embodiments may be made without departing from the scopeof the invention as hereinafter claimed along with their legalequivalents. In addition, features from one embodiment may be combinedwith features of another embodiment while still being encompassed withinthe scope of the invention as contemplated by the inventors.

1. A method of accessing data in a memory, comprising: allocating acircular buffer region of the memory for use by an autonomous circularbuffer controller; transferring input data elements to the circularbuffer region at subsequent input locations pointed at by an inputpointer; and transferring output data elements from the circular bufferregion at subsequent output locations pointed at by an output pointer;wherein each of the input pointer and the output pointer are configuredto: update to point to a next data element location in the circularbuffer region responsive to access to a current data element location;and wrap around to a beginning address of the circular buffer regionresponsive to an ending address of the circular buffer region beingreached.
 2. The method of claim 1, wherein: the input pointer and theoutput pointer being equal indicates that the circular buffer region isempty; and the input pointer and the output pointer being unequalindicates that the circular buffer region includes valid data.
 3. Themethod of claim 1, wherein the transferring input data elements and thetransferring output data elements both occur while the circular bufferregion is not empty and not full.
 4. The method of claim 1, whereintransferring input data elements to the circular buffer region atsubsequent input locations pointed at by an input pointer comprisestransferring input data elements from a register interface to thecircular buffer region.
 5. The method of claim 1, wherein transferringoutput data elements from the circular buffer region at subsequentoutput locations pointed at by an output pointer comprises receiving anevent notification indicating that a peripheral is available.
 6. Asystem, comprising: a first interface for communicating on a first busfor operable coupling with one or more peripheral devices and a hostprocessor; a second interface for communicating on a second bus foroperable coupling with a memory; and an autonomous circular buffercontroller for defining and accessing a circular buffer region of thememory and configured to: control a head pointer for stepping throughthe circular buffer region and wrapping around from an ending address toa beginning address; control a tail pointer for stepping through thecircular buffer region and wrapping around from the ending address tothe beginning address; move a first data element from the firstinterface to a location in the circular buffer region pointed at by thehead pointer; and move a second data element from a location in thecircular buffer region pointed at by the tail pointer to the firstinterface.
 7. The system of claim 6, further comprising the hostprocessor and the one or more peripheral devices and wherein: the firstdata element is received from at least one peripheral device of the oneor more peripheral devices; and the second data element is sent to thehost processor.
 8. The system of claim 6, further comprising the hostprocessor and the one or more peripheral devices and wherein: the firstdata element is received from the host processor; and the second dataelement is sent to at least one peripheral device of the one or moreperipheral devices.
 9. The system of claim 8, wherein the one or moreperipheral devices are selected from a group comprising: a universalsynchronous/asynchronous receiver-transmitter, a universal asynchronousreceiver-transmitter, a digital-to-analog converter, ananalog-to-digital converter, a serial-peripheral-interface, a two-wireinterface, and an inter-integrated circuit bus.
 10. The system of claim6, wherein the autonomous circular buffer controller is configured toreceive an indicator of a direct memory access request for one of theone or more peripheral devices.
 11. The system of claim 6, wherein thefirst interface, second interface, and autonomous circular buffercontroller are incorporated into a peripheral device.
 12. A system, thesystem comprising: a host processor; one or more peripheral devices; afirst interface for communicating on a first bus for operable couplingwith the one or more peripheral devices and the host processor; and anautonomous circular buffer controller for defining and accessing acircular buffer region a memory and configured to: control a headpointer for stepping through the circular buffer region and wrappingaround from an ending address to a beginning address; control a tailpointer for stepping through the circular buffer region and wrappingaround from the ending address to the beginning address; move a firstdata element from a location in the circular buffer region pointed at bythe tail pointer to the first interface.
 13. The system of claim 12,wherein the host processor is configured to write the first data elementto the circular buffer region.
 14. The system of claim 13, wherein theautonomous circular buffer controller moves the first data element fromthe location in the circular buffer region responsive to an interrupt.15. The system of claim 12, wherein the autonomous circular buffercontroller is configured to move a second data element from the one ormore peripheral devices to the circular buffer region pointed at by thetail pointer and notify a CPU that data is available in the circularbuffer region.
 16. The system of claim 15, wherein the autonomouscircular buffer controller includes one or more status registers thatare accessible by the CPU.
 17. The system of claim 16, wherein a firstvalue stored in the one or more status registers is indicative of thesize of the second data element.
 18. A system, comprising: a hostprocessor; a first peripheral device; and a second peripheral device,the second peripheral device comprising a first interface configured tocommunicate on a bus operably coupled to the host processor and thefirst peripheral device, wherein the second peripheral device isconfigured to provide a multichannel autonomous communication pathbetween the host processor and first peripheral device.
 19. The systemof claim 18, wherein the host processor, the first peripheral and secondperipheral devices are incorporated with an embedded system.
 20. Thesystem of claim 19, wherein the host processor is part of amicrocontroller and the first peripheral device is a digital-to-analogconverter or an analog-to-digital converter.